PI: Apan Qasem

Students: Michael Jason Cade, Schmichael Chen

Funding: IBM

Period: 03/15/08 - 02/14/09

The emergence of multi-core systems opens new opportunities for thread-level parallelism and dramatically increases the performance potential of applications running on these systems. However, the state of the art in performance enhancing software is far from adequate in regards to the exploitation of hardware features on this complex new architecture. As a result, much of the performance capabilities of multi-core systems are yet to be realized. Our research addresses one facet of this problem by exploring the relationship between data-locality and parallelism in the context of multi-core architectures where one or more levels of cache are shared among the different cores. We are developing a compiler model for determining a profitable synchronization interval for concurrent threads that interact in a producer-consumer fashion.